Merge pull request #2201 from folkertdev/rustdocflags

fix CI after LLVM bump

Author: sayantn

ci/dox.sh

@@ -22,6 +22,7 @@ dox() {
     export CARGO_UNSTABLE_BUILD_STD=core
     # amdgpu needs a target-cpu, any is fine
     export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx900"
+    export RUSTDOCFLAGS="${RUSTDOCFLAGS} -Ctarget-cpu=gfx900"
   fi
 
   cargo build --verbose --target "${1}" --manifest-path crates/core_arch/Cargo.toml

ci/run.sh

@@ -82,7 +82,7 @@ cargo_test() {
             else
               dir="debug"
             fi
-            export CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/$dir/deps::."
+            export CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime -Wexceptions --dir /checkout/target/wasm32-wasip1/$dir/build::."
             cmd="$cmd --nocapture"
             ;;
     esac

crates/core_arch/src/aarch64/sve/mod.rs

@@ -39,7 +39,7 @@ impl<T> SveInto<T> for T {
 macro_rules! impl_sve_type {
     ($(($v:vis, $elem_type:ty, $name:ident, $elt:literal))*) => ($(
         #[doc = concat!("Scalable vector of type ", stringify!($elem_type))]
-        #[derive(Clone, Copy, Debug)]
+        #[derive(Clone, Copy)]
         #[rustc_scalable_vector($elt)]
         #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
         $v struct $name($elem_type);
@@ -52,21 +52,21 @@ macro_rules! impl_sve_tuple_type {
     )*);
     (@ ($v:vis, $vec_type:ty, 2, $name:ident)) => (
         #[doc = concat!("Two-element tuple of scalable vectors of type ", stringify!($vec_type))]
-        #[derive(Clone, Copy, Debug)]
+        #[derive(Clone, Copy)]
         #[rustc_scalable_vector]
         #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
         $v struct $name($vec_type, $vec_type);
     );
     (@ ($v:vis, $vec_type:ty, 3, $name:ident)) => (
         #[doc = concat!("Three-element tuple of scalable vectors of type ", stringify!($vec_type))]
-        #[derive(Clone, Copy, Debug)]
+        #[derive(Clone, Copy)]
         #[rustc_scalable_vector]
         #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
         $v struct $name($vec_type, $vec_type, $vec_type);
     );
     (@ ($v:vis, $vec_type:ty, 4, $name:ident)) => (
         #[doc = concat!("Four-element tuple of scalable vectors of type ", stringify!($vec_type))]
-        #[derive(Clone, Copy, Debug)]
+        #[derive(Clone, Copy)]
         #[rustc_scalable_vector]
         #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
         $v struct $name($vec_type, $vec_type, $vec_type, $vec_type);

crates/core_arch/src/amdgpu/mod.rs

@@ -351,15 +351,16 @@ pub unsafe fn sched_barrier<const MASK: u32>() {
 /// Combining multiple `sched_group_barrier` intrinsics enables an ordering of specific instruction types during instruction scheduling.
 /// For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions.
 ///
-/// ```rust
+/// ```ignore
 /// // 1 VMEM read
-/// sched_group_barrier::<32, 1, 0>()
+/// sched_group_barrier::<32, 1, 0>();
 /// // 1 VALU
-/// sched_group_barrier::<2, 1, 0>()
+/// sched_group_barrier::<2, 1, 0>();
 /// // 5 MFMA
-/// sched_group_barrier::<8, 5, 0>()
+/// sched_group_barrier::<8, 5, 0>();
 /// ```
 ///
+#[doc(cfg(target_arch = "amdgpu"))]
 #[doc = include_str!("intrinsic_is_convergent.md")]
 #[inline]
 #[unstable(feature = "stdarch_amdgpu", issue = "149988")]