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1. systolic-array-accelerator systolic-array-accelerator Public

   4×4 weight-stationary systolic array AI accelerator — Python golden model → RTL → FPGA → ASIC (Sky130)

   Verilog 2

2. AutoAnalog AutoAnalog Public

   AI-Assisted Design and Optimization Platform for a Two-Stage CMOS Operational Amplifier

   Python 1

3. verilog-rtl-projects verilog-rtl-projects Public

   A progressive series of Verilog RTL designs - combinational logic, FSMs, datapaths & more.

   Verilog