earlgrey: Add SPI mux support - #412
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| pub struct SwitchMuxFinOp { | ||
| /// A bitmap indicating which SPI flash devices are accessible. | ||
| /// Bit `i` set to 1 means Flash device `i` is accessible (e.g., bit 0 = 0x1 for Host 0, bit 1 = 0x2 for Host 1). | ||
| pub accessible_flash_bitmap: u32, |
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Nit: Could u8 be sufficient for the use case here?
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Yes you're right. Changed to u8.
| .map_err(ErrorCode::from)?; | ||
| let _ = sleep_until(SystemClock::now() + RESET_HOLD_DELAY); | ||
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| // Step 2: Switch MUX selection channel (LOW for Host 0, HIGH for Host 1). |
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Should we use the inverse logic (HIGH for Host 0 and LOW for Host 1) for the MUX selection? In the integration block diagram, Earlgrey's SPI HOST 0 is connected to SPI EEPROM 0, while SPI HOST 1 is connected to SPI EEPROM 1. When the SPI_MUX_CTRL is pulled low, it directs the main CPU complex to SPI EEPROM 0. This implies that Earlgrey has exclusive access to SPI EEPROM 1, and the associated SPI HOST is 1.
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Nice catch. Tried to use more descriptive names to avoid mental computation and confusion in the future: HostCpu0Earlgrey1, HostCpu1Earlgrey0
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Add a dedicated control channel and multi-channel IPC infrastructure to
coordinate SPI MUX switching and flash access in Earlgrey firmware.
Key changes:
1. Control Plane Isolation:
- Introduce `SPI_FLASH_MUX_SERVICE` and `FlashMuxClient` in
`target/earlgrey/services/platform/flash_mux.rs`.
- Add opcodes `IPC_OP_FLASH_SWITCH_MUX_NOTICE` (quiesce access) and
`IPC_OP_FLASH_SWITCH_MUX_FIN_NOTICE` (re-initialize 4-Byte address mode).
- Keep generic `services/flash` 100% clean of platform-specific MUX logic.
- Update `PlatformServer::switch_mux` to use `FlashMuxClient` and `SpiMuxRoute`.
2. Multi-Channel Flash Server:
- Provide dedicated data channels `SPI_FLASH0_SERVICE` and `SPI_FLASH1_SERVICE`.
- Provide dynamic data channel `SPI_GENERIC_FLASH_SERVICE` that routes to
the active flash device.
- Isolate internal `EFLASH_SERVICE` from MUX switching operations.
- Directly reject inactive or quiesced channels with `FLASH_GENERIC_INACCESSIBLE`.
3. Verification:
- Update `target/earlgrey/tests/spi_flash` with E2E hardware verification.
- Verify dedicated channel rejection, quiescence rejection, and 4-Byte
address mode operation on the CW340 FPGA target.
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