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Refactor - #17
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Refactor#17
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- Introduced a new `Trail` structure to manage variable assignments and backtracking. - Updated `propagate` functions to utilize the trail for recording variable assignments. - Implemented caching for branch applications to optimize performance. - Refactored branching logic to support trail recording during branching decisions. - Enhanced the `record_solved_leaf!` function to extract successful paths from the trail. - Added new files for branch caching and optimal branching rule selection. - Updated tests to validate new trail functionality and branching improvements.
- Removed the `parse_verilog_to_circuit` function from the `CircuitIO` module. - Updated the `verilog_to_circuit` function to directly use the content read from the file. - Added a new `circuit_analysis.jl` file to implement tensor network information extraction and circuit analysis functions. - Enhanced the `setup_problem` function to include tensor depth, fanin, and fanout information. - Updated tests to validate the new circuit analysis functionalities.
- Removed the `TensorNetworkInfo` structure and related functions from `circuit_analysis.jl`. - Updated the `setup_from_sat` function to directly compute tensor data and circuit metadata. - Enhanced the `setup_problem` function to include tensor symbols for circuit gate types. - Simplified the `setup_from_tensor_network` function to streamline tensor network setup. - Adjusted function signatures to improve clarity and reduce redundancy.
- Introduced `MinGammaSelector` for improved branching strategy in `factoring.jl`. - Updated the `solve` function to utilize `bbsat!` for better performance and clarity. - Refactored region handling in `region.jl` to simplify variable management. - Enhanced `RegionCache` structure to optimize caching of configurations. - Improved propagation logic in `propagate.jl` for efficiency. - Updated tests to reflect changes in region variable handling.
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