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4 changes: 4 additions & 0 deletions src/fdt/node.rs
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,10 @@ impl<'a> Node<'a> for FdtNode<'a> {
parent_address_space: self.address_space(),
}
}

fn parent_address_space(self) -> AddressSpaceProperties {
self.parent_address_space
}
}

impl<'a> FdtNode<'a> {
Expand Down
6 changes: 6 additions & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,7 @@ use core::ops::{BitOr, Shl};
use zerocopy::big_endian;

use crate::error::{PropertyError, StandardError};
use crate::standard::AddressSpaceProperties;
pub use crate::values::{
FdtStringListIterator, FromPropertyValue, PropEncodedArrayIterator, ToPropertyValue,
};
Expand Down Expand Up @@ -244,6 +245,11 @@ pub trait Node<'a>: Copy {
/// assert!(children.next().is_none());
/// ```
fn children(self) -> Self::Children;

/// Returns the `#address-cells` and `#size-cells` properties of this
/// node's parent node.
#[must_use]
fn parent_address_space(self) -> AddressSpaceProperties;
}

/// A property of a device tree node.
Expand Down
4 changes: 4 additions & 0 deletions src/model/node.rs
Original file line number Diff line number Diff line change
Expand Up @@ -118,6 +118,10 @@ impl<'a> Node<'a> for DeviceTreeNodeRef<'a> {
parent_address_space: self.address_space(),
}
}

fn parent_address_space(self) -> AddressSpaceProperties {
self.parent_address_space
}
}

mod private {
Expand Down
26 changes: 14 additions & 12 deletions src/standard.rs
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@ pub use self::ranges::Range;
pub use self::reg::Reg;
pub use self::status::Status;
use crate::error::{PropertyError, StandardError};
use crate::fdt::FdtNode;
use crate::{Node, Property};

pub(crate) const DEFAULT_ADDRESS_CELLS: u32 = 2;
Expand Down Expand Up @@ -157,20 +156,17 @@ pub trait NodeStandard<'a>: Node<'a> {
fn dma_coherent(self) -> bool {
self.property("dma-coherent").is_some()
}
}

impl<'a, T: Node<'a>> NodeStandard<'a> for T {}

impl<'a> FdtNode<'a> {
/// Returns the value of the standard `reg` property.
///
/// # Errors
///
/// Returns an error if the size of the value isn't a multiple of the
/// expected number of address and size cells.
pub fn reg(self) -> Result<Option<impl Iterator<Item = Reg<'a>> + 'a>, PropertyError> {
let address_cells = self.parent_address_space.address_cells as usize;
let size_cells = self.parent_address_space.size_cells as usize;
fn reg(self) -> Result<Option<impl Iterator<Item = Reg<'a>> + use<'a, Self>>, PropertyError> {
let parent_address_space = self.parent_address_space();
let address_cells = parent_address_space.address_cells as usize;
let size_cells = parent_address_space.size_cells as usize;
if let Some(property) = self.property("reg") {
Ok(Some(
property
Expand All @@ -188,13 +184,15 @@ impl<'a> FdtNode<'a> {
///
/// Returns an error if the size of the value isn't a multiple of the
/// expected number of cells.
pub fn ranges(self) -> Result<Option<impl Iterator<Item = Range<'a>> + 'a>, PropertyError> {
fn ranges(
self,
) -> Result<Option<impl Iterator<Item = Range<'a>> + use<'a, Self>>, PropertyError> {
if let Some(property) = self.property("ranges") {
Ok(Some(
property
.as_prop_encoded_array([
self.address_cells().unwrap_or(DEFAULT_ADDRESS_CELLS) as usize,
self.parent_address_space.address_cells as usize,
self.parent_address_space().address_cells as usize,
self.size_cells().unwrap_or(DEFAULT_SIZE_CELLS) as usize,
])?
.map(Range::from_cells),
Expand All @@ -210,13 +208,15 @@ impl<'a> FdtNode<'a> {
///
/// Returns an error if the size of the value isn't a multiple of the
/// expected number of cells.
pub fn dma_ranges(self) -> Result<Option<impl Iterator<Item = Range<'a>> + 'a>, PropertyError> {
fn dma_ranges(
self,
) -> Result<Option<impl Iterator<Item = Range<'a>> + use<'a, Self>>, PropertyError> {
if let Some(property) = self.property("dma-ranges") {
Ok(Some(
property
.as_prop_encoded_array([
self.address_cells().unwrap_or(DEFAULT_ADDRESS_CELLS) as usize,
self.parent_address_space.address_cells as usize,
self.parent_address_space().address_cells as usize,
self.size_cells().unwrap_or(DEFAULT_SIZE_CELLS) as usize,
])?
.map(Range::from_cells),
Expand All @@ -227,6 +227,8 @@ impl<'a> FdtNode<'a> {
}
}

impl<'a, T: Node<'a>> NodeStandard<'a> for T {}

/// The `#address-cells` and `#size-cells` properties of a node.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub struct AddressSpaceProperties {
Expand Down
5 changes: 2 additions & 3 deletions src/standard/cpus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use core::ops::Deref;

use crate::error::{PropertyError, StandardError};
use crate::fdt::{Fdt, FdtNode};
use crate::standard::NodeStandard;
use crate::values::FdtStringListIterator;
use crate::{Cells, Node, Property};

Expand Down Expand Up @@ -106,9 +107,7 @@ impl<'a, N: Node<'a>> Cpu<N> {
.map(Property::value_as)
.transpose()
}
}

impl<'a> Cpu<FdtNode<'a>> {
/// Returns an iterator over the IDs of the CPU, from the standard `reg`
/// property.
///
Expand All @@ -117,7 +116,7 @@ impl<'a> Cpu<FdtNode<'a>> {
/// Returns an error if a property's name or value cannot be read, or the
/// `reg` property is missing, or the size of the value isn't a multiple of
/// the expected number of address and size cells.
pub fn ids(self) -> Result<impl Iterator<Item = Cells<'a>> + 'a, StandardError> {
pub fn ids(self) -> Result<impl Iterator<Item = Cells<'a>> + use<'a, N>, StandardError> {
Ok(self
.node
.reg()?
Expand Down
11 changes: 6 additions & 5 deletions src/standard/memory.rs
Original file line number Diff line number Diff line change
Expand Up @@ -182,18 +182,19 @@ impl<'a, N: Node<'a>> ReservedMemory<N> {
pub fn reusable(self) -> bool {
self.node.property("reusable").is_some()
}
}

impl<'a> ReservedMemory<FdtNode<'a>> {
/// Returns the value of the standard `alloc-ranges` property.
///
/// # Errors
///
/// Returns an error if the size of the value isn't a multiple of the
/// expected number of address and size cells.
pub fn alloc_ranges(self) -> Result<Option<impl Iterator<Item = Reg<'a>> + 'a>, StandardError> {
let address_cells = self.node.parent_address_space.address_cells as usize;
let size_cells = self.node.parent_address_space.size_cells as usize;
pub fn alloc_ranges(
self,
) -> Result<Option<impl Iterator<Item = Reg<'a>> + use<'a, N>>, StandardError> {
let parent_address_space = self.node.parent_address_space();
let address_cells = parent_address_space.address_cells as usize;
let size_cells = parent_address_space.size_cells as usize;
if let Some(property) = self.node.property("alloc-ranges") {
Ok(Some(
property
Expand Down
79 changes: 79 additions & 0 deletions tests/model.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,9 @@

#![cfg(feature = "write")]

use dtoolkit::fdt::Fdt;
use dtoolkit::model::{DeviceTree, DeviceTreeNode, DeviceTreeProperty};
use dtoolkit::standard::{AddressSpaceProperties, NodeStandard};
use dtoolkit::{Node, Property};

#[test]
Expand Down Expand Up @@ -183,3 +185,80 @@ fn device_tree_format() {
"
);
}

#[test]
fn parent_address_space() {
let dtb = include_bytes!("dtb/test_props.dtb");
let fdt = Fdt::new(dtb).unwrap();
let tree = DeviceTree::from_fdt(&fdt);

let standard_props_node = tree.find_node("/standard-props").unwrap();
assert_eq!(
standard_props_node.parent_address_space(),
AddressSpaceProperties {
address_cells: 2,
size_cells: 2,
}
);
}

#[test]
fn reg() {
let dtb = include_bytes!("dtb/test_props.dtb");
let fdt = Fdt::new(dtb).unwrap();
let tree = DeviceTree::from_fdt(&fdt);

let standard_props_node = tree.find_node("/standard-props").unwrap();
let reg = standard_props_node
.reg()
.unwrap()
.unwrap()
.collect::<Vec<_>>();
assert_eq!(reg.len(), 2);
assert_eq!(reg[0].address::<u64>().unwrap(), 0x1234_5678_0000_3000);
assert_eq!(reg[0].size::<u64>().unwrap(), 32);
assert_eq!(reg[1].address::<u64>().unwrap(), 0xfe00);
assert_eq!(reg[1].size::<u64>().unwrap(), 256);
}

#[test]
fn ranges() {
let dtb = include_bytes!("dtb/test_props.dtb");
let fdt = Fdt::new(dtb).unwrap();
let tree = DeviceTree::from_fdt(&fdt);

let standard_props_node = tree.find_node("/standard-props").unwrap();
let ranges = standard_props_node
.ranges()
.unwrap()
.unwrap()
.collect::<Vec<_>>();
assert_eq!(ranges.len(), 1);
assert_eq!(ranges[0].child_bus_address::<u32>().unwrap(), 0x1111_0000);
assert_eq!(
ranges[0].parent_bus_address::<u64>().unwrap(),
0x2222_0000_3333_0000
);
assert_eq!(ranges[0].length::<u32>().unwrap(), 0x4444_0000);
}

#[test]
fn dma_ranges() {
let dtb = include_bytes!("dtb/test_props.dtb");
let fdt = Fdt::new(dtb).unwrap();
let tree = DeviceTree::from_fdt(&fdt);

let standard_props_node = tree.find_node("/standard-props").unwrap();
let dma_ranges = standard_props_node
.dma_ranges()
.unwrap()
.unwrap()
.collect::<Vec<_>>();
assert_eq!(dma_ranges.len(), 1);
assert_eq!(dma_ranges[0].child_bus_address::<u32>().unwrap(), 0xaaaa);
assert_eq!(
dma_ranges[0].parent_bus_address::<u64>().unwrap(),
0xbbbb_0000_cccc
);
assert_eq!(dma_ranges[0].length::<u32>().unwrap(), 0xdddd);
}
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