[CORE] Fix some logic errors reported in #4214 - #4261
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1. `||` has higher precedence than `?:`, TI bit locates at bit2. 2. `ED` is a `reg64_t *` and it gets scaled by `sizeof(reg64_t)`. 3. Use `rex.w?7:3` to whether address is aligned.
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||has higher precedence than?:, TI bit locates at bit2.EDis areg64_t *and it gets scaled bysizeof(reg64_t).Use
rex.w?7:3to check whether address is aligned or not.