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arch/mips: Add basic support for MIPS Creator CI20 board
This commit introduces a rudimentary architecture and board port for the MIPS Creator CI20, featuring the dual core Ingenic JZ4780 SoC (MIPS32). Included in this initial implementation: - Basic architectural initialization and startup code for the JZ4780 Core 0. - Minimal configuration required to execute from RAM. - Early UART/serial console support for basic debugging and NSH output. - Minimal board-specific configuration for the CI20 target. - Console output is routed via UART0 on the expansion header. This establishes basic support for running NuttX on the MIPS CI20. Further peripherals, optimization, and extended documentation are left for future iterations or community contributions. Build and Runtime Deployment Info: ---------------------------------- The baseline can be configured, compiled using the MIPS MTI toolchain, and loaded via U-Boot using the following commands (replace <tftp_dir> with your local TFTP root directory). ./tools/configure.sh -l ci20/nsh make CROSSDEV=mips-mti-elf- mkimage -A mips -O linux -T kernel -C none -a 0x80000180 -e 0x800004ac \ -n "nx" -d nuttx.bin <tftp_dir>/nuttx.umg Note: U-Boot must be properly configured for networking (e.g., valid ipaddr, serverip, and ethaddr environment variables) to fetch the image over TFTP. Run this from U-Boot prompt: tftp nuttx.umg && bootm $fileaddr Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
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‎Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/ci20.jpg‎

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‎Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst‎

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=================
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MIPS Creator CI20
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=================
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.. tags:: arch:mips, chip:jz4780
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.. figure:: ci20.jpg
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:figwidth: 100%
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:align: center
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:alt: The MIPS Creator CI20 V2.0
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The MIPS Creator CI20 V2.0
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Supported Features
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==================
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* Single 1.2GHz MIPS32 processor
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* UART0 on Raspberry PI connector
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* 256MiB DRAM
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Configurations
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==============
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.. important::
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U-Boot must be properly configured for networking (e.g., valid ``ipaddr``,
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``serverip``, and ``ethaddr`` environment variables) to fetch the image over TFTP.
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NuttX is loaded via U-Boot using TFTP (replace ``<tftp_dir>`` with your local
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TFTP root directory).
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You can use the following command to configure the NuttX build:
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.. code-block:: shell
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./tools/configure.sh -l ci20/nsh
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make CROSSDEV=mips-mti-elf-
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mkimage -A mips -O linux -T kernel -C none -a 0x80000180 -e 0x800004ac \
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-n "nx" -d nuttx.bin <tftp_dir>/nuttx.umg
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Run this from U-Boot prompt:
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.. code-block:: shell
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tftp nuttx.umg && bootm $fileaddr
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nsh
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---
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Basic serial console access to the NSH shell.
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.. note::
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Connect USB cable from your PC to UART0 pins on the Raspberry PI connector.
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Then use some serial console client (minicom, picocom, teraterm, etc)
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configured to 115200 8n1 without software or hardware flow control.

‎Documentation/platforms/mips/jz4780/index.rst‎

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==============
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Ingenic JZ4780
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==============
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MIPS32r2 architecture.
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The basic port is functional and a NuttShell (NSH) configuration is available.
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Supported Boards
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================
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.. toctree::
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:glob:
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:maxdepth: 1
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boards/*/*

‎arch/mips/Kconfig‎

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---help---
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Microchip PIC32MZ (MIPS32)
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config ARCH_CHIP_JZ4780
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bool "JZ4780"
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select ARCH_MIPS32
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select ARCH_MIPS_XBURST1
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select ARCH_HAVE_IRQPRIO
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SERIAL_TERMIOS
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select MIPS32_HAVE_DCACHE
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select MIPS32_HAVE_ICACHE
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select MIPS32_USE_WAIT_INSTRUCTION
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select MIPS32_USE_SYSCALL_INSTRUCTION
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---help---
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Ingenic JZ4780 (MIPS32)
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config ARCH_CHIP_MIPS_CUSTOM
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bool "Custom MIPS chip"
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select ARCH_CHIP_CUSTOM
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default n
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select ARCH_HAVE_MICROMIPS
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config ARCH_MIPS_XBURST1
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bool
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default n
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config ARCH_HAVE_EIC
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bool
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default n
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string
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default "pic32mx" if ARCH_CHIP_PIC32MX
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default "pic32mz" if ARCH_CHIP_PIC32MZ
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default "jz4780" if ARCH_CHIP_JZ4780
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source "arch/mips/src/common/Kconfig"
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source "arch/mips/src/mips32/Kconfig"
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source "arch/mips/src/pic32mx/Kconfig"
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source "arch/mips/src/pic32mz/Kconfig"
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source "arch/mips/src/jz4780/Kconfig"
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endif

‎arch/mips/include/jz4780/chip.h‎

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/****************************************************************************
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* arch/mips/include/jz4780/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H
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#define __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CKPCR 0xB0003040
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#define CKPCR_CK32CTL_RTCLK (3 << 1)
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#define JZINTC_BASE 0xB0001000
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#define ICMSR0 (JZINTC_BASE + 0x08)
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#define ICMCR0 (JZINTC_BASE + 0x0C)
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#define ICPR0 (JZINTC_BASE + 0x10)
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#define ICMSR1 (JZINTC_BASE + 0x28)
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#define ICMCR1 (JZINTC_BASE + 0x2C)
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#define ICPR1 (JZINTC_BASE + 0x30)
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#define JZTMR_BASE 0xB0002000
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#define WD_TDR (JZTMR_BASE + 0x00) // u16: Watchdog Timer Data
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#define WD_TCER (JZTMR_BASE + 0x04) // u8 : Watchdog Counter Enable
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#define WD_TCNT (JZTMR_BASE + 0x08) // u16: Watchdog Timer Counter
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#define WD_TCSR (JZTMR_BASE + 0x0C) // u16: Watchdog Timer Control
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#define TCSR_PRESCALE(x) ((x) << 3)
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#define TCSR_DIV_16 2
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#define TCSR_EXT_EN (1 << 2)
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#define TCSR_RTC_EN (1 << 1)
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#define TCSR_PCK_EN (1 << 0)
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#define TCER_TCEN (1 << 0)
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#define OSTDR (JZTMR_BASE + 0xe0)
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#define OSTCNTL (JZTMR_BASE + 0xe4)
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#define OSTCNTH (JZTMR_BASE + 0xe8)
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#define OSTCSR (JZTMR_BASE + 0xec)
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#define TESR (JZTMR_BASE + 0x14)
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#define TESR_OSTEN (1 << 15)
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#define TESR_TCEN(n) (1 << (n))
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#define TMSR (JZTMR_BASE + 0x34)
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#define TMCR (JZTMR_BASE + 0x38)
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#define TMCR_OSTMCL (1 << 15)
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#define TMCR_FMCL5 (1 << 5)
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#define TMCR_FMCL(n) (1 << (n))
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#define TFR (JZTMR_BASE + 0x20)
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#define TFCR (JZTMR_BASE + 0x28)
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#define TFCR_OSTFCL (1 << 15)
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#define TFCR_FFCL5 (1 << 5)
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#define TFCR_FFCL(n) (1 << (n))
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#define TCNT(n) (JZTMR_BASE + 0x48 + (n)*0x10)
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#define TCSR(n) (JZTMR_BASE + 0x4C + (n)*0x10)
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#define TDFR(n) (JZTMR_BASE + 0x40 + (n)*0x10)
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#define TICKS_PER_MS (48000/16)
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#define CHIP_JZ4780 1
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#define CHIP_NPORTS 6 /* 6 ports (A-F) */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: jz_physregaddr
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*
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* Description:
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* Give the virtual address of a register, return the physical address of
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* the register
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*
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****************************************************************************/
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uintptr_t jz_physregaddr(uintptr_t virtregaddr);
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/****************************************************************************
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* Name: jz_physramaddr
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*
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* Description:
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* Give the virtual address of a RAM memory location, return the physical
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* address of that location.
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*
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****************************************************************************/
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uintptr_t jz_physramaddr(uintptr_t vramaddr);
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/****************************************************************************
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* Name: jz_virtramaddr
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*
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* Description:
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* Give the physical address of a RAM memory location, return the virtual
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* address of that location.
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*
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****************************************************************************/
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uintptr_t jz_virtramaddr(uintptr_t physramaddr);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H */

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