Pinned Loading

1. flashattn-accelerator flashattn-accelerator Public

   Stateful INT8 FlashAttention accelerator in SystemVerilog | 16×16 systolic array, 4Q:2KV GQA, persistent KV cache, AXI4 DMA & AXI4-Lite control.

   SystemVerilog 3

2. mac-accel-cdc mac-accel-cdc Public

   Dual-clock Vector MAC with AXI DMA, RID-indexed ROB, CDC/formal verification, and OpenROAD RTL-to-GDS implementation.

   Verilog

3. memory-controller-rtl memory-controller-rtl Public

   Synthesizable banked DRAM controller: scheduling, ordering, formal verification, performance analysis, and ASIC synthesis evidence

   Tcl

4. rv32i-core rv32i-core Public

   RV32I 5-stage pipeline processor in Verilog — caches, branch predictor, AXI4-Lite

   Verilog