I build computer systems from discrete MOSFETs through full ASIC tapeout.

I am a Computer Engineering junior at the University of Pennsylvania specializing in computer architecture, RTL design, and hardware verification. I thrive at the intersection of hardware and software—architecting boards, writing SystemVerilog, and building the constrained-random environments that prove them.

• Currently: Hardware Research Engineer (Fall 2026) at Fluid Silicon (RTL & Emulation) & Software Engineer at Aragorn AI.
• Previously: Hardware & Firmware Engineer at Vero Electric (PCB design & Board bring-up).

• LibreLane — Fixes chk.rpt so pre- and post-synth errors both count; · #1016
• LibreLane — Fixes Yosys ≥ 0.68 abc -fast so synthesis does not die; · #1015
• Verilator — Fixes Linux peak-memory stats so --stats matches real RSS · #8070
• OpenROAD — Fixes MINWIDTH WRONGDIRECTION so production LEF files load · #11107
• OpenFPGA — Fixes contribution and interconnect docs so syntax matches the parser · #2682 · #2683

Build log →

Highlights below — all projects → · full résumé →

Hardware

• Tomato (GitHub) — custom 32-bit CPU · discrete logic through PCB tapeout
• 16×4 SRAM — Full-Custom Analog Design — 6T macro in 22 nm HP · StrongARM sense amp · 4.571 GHz fmax
• SPICE Automation Framework — NGSpice fmax binary search · parametric PPA sweeps · JSON/CSV/Markdown reports
• 16-Bit Mac Unit (Sky130) — BFloat16 MAC · OpenLane · TinyTapeout
• NASDAQ ITCH 5.0 Hardware Parser — market-data FPGA on Artix-7 · cocotb
• 100 Mbps UDP/IP Stack — RMII/MAC/ARP/IP/UDP · sub-200 ns loopback
• 8-Bit Discrete Transistor ALU — 3,488 MOSFETs · 1.24M+ automated test vectors

Tools & software

• Mango Tools — offline CLI for PDF, media & images
• Orange Metrics API — Vivado & OpenLane PPA ingestion · FastAPI · PostgreSQL · Docker
• QueuePaste — macOS clipboard queue · ⌥ Space to paste
• Music & You — personality from Spotify listening · Next.js · scikit-learn
• UniBridge Ghana — university admissions platform · FastAPI · PostgreSQL
• SVD Compression Engine — cache-optimized matrix ops from scratch

• Aragorn AI — Software Engineering Intern · Present · production backends & APIs
• Fluid Silicon Inc. — Hardware Research Engineer Intern · Pennovation Center · Fall 2026
• Howard STEM Achievers — STEM Instructor · AR/VR · Jun–Jul 2026
• Vero Electric — Hardware & Firmware Engineer · battery management infrastructure · May–Aug 2026
• Fife-Penn — Programming & Engineering Instructor · Feb–May 2025
• Penn Engineering — CIS 1100 Teaching Assistant

Hardware · SystemVerilog · UVM / SVA · cocotb · Verilator · SymbiYosys · Questa · Vivado · RISC-V · KiCad · LibreLane / OpenROAD / Yosys / Sky130 · NGSpice · embedded C/C++ · SPI/I²C
Software · Python · C/C++ · TypeScript · FastAPI · PostgreSQL · Pytest · Docker
Practice · constrained-random + golden-model scoreboards · formal (SymbiYosys) · timing closure · board bring-up

Source for tmarhguy.com. Setup, commands, and credits: docs/getting-started.md.

Licensed under the MIT License.