systolic-array

Algebraic enhancements for GEMM & AI accelerators

Minimal TPU implementation with 8x8 systolic array and PyTorch integration

End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference

A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication

Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.

SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations

Modular systolic array with software interface

Small-scale FPGA-based Neural Processing Unit (CNN Accelerator) with INT8 systolic array matrix multiplication in Verilog.

course materials of Hardware Accelerator course, a practical course on hardware accelerators: CNN accelerators, systolic arrays, CUDA, quantization, pruning, Vivado, Timeloop/Accelergy, and MAESTRO. Spring 2025, Shahid Beheshti University

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

Hardware accelerator for 2D convolution using an 8×8 weight-stationary systolic array with split-kernel support, dual-port SRAM architecture, and DMA-based streaming

Parameterized matrix-multiply accelerator (FPGA), built three ways: sequential, systolic, and systolic with BRAM. SystemVerilog RTL verified in cocotb against a Python golden model under randomized backpressure, and characterized for PPA across three architectures and five sizes on a Xilinx ZCU104.

Verilog implementation of a Torus-based systolic array accelerator for matrix multiplication.

INT8 inference accelerator on a Basys 3 FPGA with a custom CPU, ISA and 4x4 weight-stationary systolic array, all built from scratch which runs a PPO-trained LunarLander policy live on the board.

RTL design of a double-buffered SRAM-to-systolic-array tiling engine with bank-conflict resolution and WS/OS data reuse (tape-out-ready sign-off)

Parameterizable output-stationary INT8 systolic MAC array in Verilog, extended into a weight-stationary 3-layer CNN accelerator (Conv1->Conv2->FC) with interlayer requantization. 20/20 samples bit-exact end-to-end vs a Python golden model; 1,900-case model sweep plus a 206-case constrained-random SV suite. CI on every push.

Stateful INT8 FlashAttention accelerator in SystemVerilog | 16×16 systolic array, 4Q:2KV GQA, persistent KV cache, AXI4 DMA & AXI4-Lite control.

An 8×8 systolic array AI accelerator implemented in SystemVerilog on Zynq UltraScale+ ZCU104, achieving 1.7 GOPS at 6 mW PL logic power (~283 GOPS/W efficiency) with full AXI-Stream PS-PL integration. Targets INT8 matrix multiplication for transformer inference acceleration, verified across behavioral, post-synthesis and implementation simulation.

A Superscalar Out-of-Order RISC-V Processor with Systolic Tensor Acceleration, Structured Sparsity, and a Congestion-Aware Network-on-Chip

4×4 weight-stationary systolic array AI accelerator — Python golden model → RTL → FPGA → ASIC (Sky130)